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| SPT9687 DUAL ULTRAFAST VOLTAGE COMPARATOR FEATURES * * * * * * Propagation Delay <2.3 ns Propagation Delay Skew <300 ps Low Power: 185 mW Low Offset 3 mV Low Feedthrough and Crosstalk Differential Latch Control APPLICATIONS * * * * * * High-Speed Instrumentation, ATE High-Speed Timing Window Comparators Line Receivers A/D Conversion Threshold Detection GENERAL DESCRIPTION The SPT9687 is a dual, very high-speed monolithic comparator. It is pin compatible with, and has improved performance over Analog Device's AD9687. The SPT9687 is designed for use in Automatic Test Equipment (ATE), highspeed instrumentation, and other high-speed comparator applications. Improvements over other sources include reduced power consumption, reduced propagation delays, and higher input impedance. The SPT9687 is available in 16-lead SOIC, 16-lead plastic DIP, 20-lead PLCC and 20-contact LCC packages over the industrial temperature range. It is also available in die form. BLOCK DIAGRAM Inverting Input Latch Enable + Noninverting Input Latch Enable A Q Output VEE VCC GNDA Q Output Q Output GNDB Q Output B Latch Enable Inverting Input B + Latch Enable Noninverting Input ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C Supply Voltages Positive Supply (VCC to GND) .................. -0.5 to +6.0 V Negative Supply (VEE to GND) ................ -6.0 to +0.5 V Ground Voltage Differential ...................... -0.5 to +0.5 V Input Voltages Input Voltage ............................................ -4.0 to +4.0 V Differential Input Voltage .......................... -5.0 to +5.0 V Input Voltage, Latch Controls ..................... V EE to 0.5 V Note: Output Output Current ...................................................... 30 mA Temperature Operating Temperature, ambient .............. -25 to +85 C junction ....................... +150 C Lead Temperature, (soldering 60 seconds) ...... +300 C Storage Temperature .............................. -65 to +150 C 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS T A = +25 C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified. PARAMETERS Input Offset Voltage Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current Input Offset Current Input Offset Current Input Common Mode Range Latch Enable Common Mode Range Open Loop Gain Input Resistance Input Capacitance Input Capacitance Power Supply Sensitivity Common Mode Rejection Ratio Positive Supply Current Negative Supply Current Positive Supply Voltage Negative Supply Voltage Power Dissipation Output High Output Low TEST CONDITIONS RS = 0 Ohms1 RS = 0 Ohms1 TMIN MIN -3 -3.5 SPT9687 TYP .5 MAX +3 +3.5 UNITS mV mV V/C A A A A V V V/V k pF pF dB dB DC ELECTRICAL CHARACTERISTICS 4 6 7 -1.0 -1.5 -2.5 -2.0 4000 60 3 1 50 50 100 85 7 27 4.75 -4.95 5.0 -5.2 185 -.98 -1.95 11 37 5.25 -5.45 250 -.81 -1.63 20 38 +1.0 +1.5 +2.5 0 TMIN (LCC Package) VCC and VEE V IV IV I I IV IV mA mA V V mW V V I OUTPUT = 0 mA 50 Ohms to -2 V 50 Ohms to -2 V I I I OUTPUT LOGIC LEVELS (ECL 10 KH Compatible) AC ELECTRICAL CHARACTERISTICS2 Propagation Delay Latch Set-up Time 10 mV OD III IV 2.0 0.6 2.3 1 ns ns SPT9687 2 3/21/97 ELECTRICAL SPECIFICATIONS T A = +25 C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL MIN SPT9687 TYP MAX UNITS AC ELECTRICAL CHARACTERISTICS2 Latch to Output Delay Latch Pulse Width Latch Hold Time Rise Time Fall Time 1RS = Source impedance. 2100 mV input step. 50 mV OD IV V IV 2 3 ns ns 0.5 1.2 1.2 ns ns ns 20% to 80% 20% to 80% V V TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests are pulsed tests; therefore, TJ = TC = TA. Figure 1 - Timing Diagram LATCH ENABLE TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range. 50% LATCH ENABLE tS DIFFERENTIAL INPUT VOLTAGE VOD tpdL OUTPUT Q 50% t pLOH tH tpL VREF VOS 50% OUTPUT Q t pdH t pLOL VIN+ = 100 mV (p-p), VOD = 50 mV The set-up and hold times are a measure of the time required for an input signal to propagate through the first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected and held; those occurring after tH will not be detected. Changes between ts and tH may not be detected. SPT9687 3 3/21/97 SWITCHING TERMS (Refer to figure 1) tpdH INPUT TO OUTPUT HIGH DELAY - The propagation delay measured from the time the input signal crosses the reference voltage ( the input offset voltage) to the 50% point of an output LOW to HIGH transition. INPUT TO OUTPUT LOW DELAY - The propagation delay measured from the time the input signal crosses the reference voltage ( the input offset voltage) to the 50% point of an output HIGH to LOW transition. GENERAL INFORMATION The SPT9687 is an ultrahigh-speed dual voltage comparator. It offers tight absolute characteristics. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. The output stage is adequate for driving terminated 50 ohm transmission lines. The SPT9687 has a complementary latch enable control for each comparator. Both should be driven by standard ECL logic levels. The dual comparator shares the same VCC and VEE connections but have separate grounds for each comparator to achieve high crosstalk rejection. Figure 2 - Internal Functional Diagram tpdL tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to 50% point of an output LOW to HIGH transition. VOD VOLTAGE OVERDRIVE - The difference between the differential input and the reference voltages. Q VIN + - tpLOL LATCH ENABLE TO OUTPUT LOW DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output HIGH to LOW transition. tH MINIMUM HOLD TIME - The minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. MINIMUM LATCH ENABLE PULSE WIDTH - The minimum time that the Latch Enable signal must be HIGH in order to acquire an input signal change. MINIMUM SET-UP TIME - The minimum time before the negative transition of the Latch Enable signal that an input signal change must be present in order to be acquired and held at the outputs. PRE AMP LATCH ECL OUT VIN Q REF 1 REF 2 CLK BUF VEE VCC GND1 LE LE GND2 TYPICAL INTERFACE CIRCUIT The typical interface circuit using the comparator is shown in figure 3. Although it needs few external components and is easy to apply, there are several conditions that should be met to achieve optimal performance. The very high operating speeds of the comparator require careful layout, decoupling of supplies, and proper design of transmission lines. Since the SPT9687 comparator is a very high frequency and high gain device, certain layout rules must be followed to avoid spurious oscillations. The comparator should be soldered to the board with component lead lengths kept as short as possible. A ground plane should be used, and the input impedance to the part should be kept as low as possible to decrease parasitic feedback. If the output board traces are longer than approximately one-half inch, microstripline techniques must be employed to prevent ringing on the output waveform. Also, the microstriplines must be terminated at the far end with the characteristic impedance of the line to prevent reflections. All supply voltage pins should be decoupled with high frequency capacitors as close to the device as possible. All ground and N/C pins should be connected to the same ground plane to further improve noise immunity and shielding. If using the SPT9687 as a single comparator, the outputs of the inactive comparator can be grounded, left open or terminated with 50 Ohms to -2 V. All outputs on the active comparator, whether used or unused, should have identical terminations to minimize ground current switching transients. Note: To ensure proper power up of the device, the input should be kept below +1.5 V during power up. SPT9687 4 3/21/97 tpL tS TIMING INFORMATION The timing diagram for the comparator is shown in figure 1. The latch enable (LE) pulse is shown at the top. If LE is high and LE low in the SPT9687, the comparator tracks the input difference voltage. When LE is driven low and LE high, the comparator outputs are latched into their existing logic states. The leading edge of the input signal (which consists of a 50 mV overdrive voltage) changes the comparator output after a time of tpdL or tpdH (Q or Q ). The input signal must be maintained for a time ts (set-up time) before the LE falling edge and LE rising edge and held for time tH after the falling edge for the comparator to accept data. After tH, the output ignores the input status until the latch is strobed again. A minimum latch pulse width of tpL is needed for strobe operation, and the output transitions occur after a time of tpLOH or tpLOL. Figure 3 - Typical Interface Circuit Figure 4 - Typical Interface With Hysteresis VCC GND VEE VO VCC GND VEE .1 F VIN .1 F VIN VREF Noninverting Input + Inverting Input Q OUTPUT Q OUTPUT VIN VRef Noninverting Input + Inverting Input Q Output Q Output LE LE RL 50 RL 50 .1 F RL 50 LE LE -2 V RL 50 -2 V 300 VLE VLE 300 -5.2 V -5.2 V .1 F 100 0.1 F 100 ECL = Represents line termination. Hysteresis is obtained by applying a DC bias to the LE pin. VLE = -1.3 V 100 mV, VLE = -1.3 V. Represents line termination. Figure 5 - Equivalent Input Circuit Figure 6 - AC Test Fixture V+ IN MONITOR VCC (+5.0 V) GND VCC 15 F L1 6 SEMI RIGID Q3 L3 R C 1 R2 Q9 6 V+ IN 0.1 F 50 50 L2 6 SEMI RIGID V 6 SEMI RIGID + IN 1 pF IN 1 pF Q11 C SEMIRIGID 6 100 SEMIRIGID + V+ Q 4 VLE Q 100 0.1 F 100 50 OUT VIN DUT LE VOUT- R V IN IN Q1 Q Q4 Q5 7 50 0.1 F 100 V L2 PRE 100 100 0.1 F 50 SAMPLING SCOPE R VIN IN V PRE 100 V R2 L1 50 50 L1 SEMI RIGID SEMI RIGID VR1 Q 2 Q 6 Q 8 Q 10 Q 12 SEMI RIGID 6 SEMI RIGID 6 6 6 15 F 15 F TANT - + + - R3 V EE R4 R5 R6 R7 LE MONITOR LE LE LE MONITOR VEE (-5.2 V) VpD (-4.0 V) Figure 7 - Output Circuit R7 240 R8 240 Figure 8 - Test Load Rz 50 Coax 50 Q24 Q23 Q Output V1 Q21 Q22 V2 Q Output RL 100 RZ 100 4.5 mA Vpd (-4.0 V) SPT9687 5 3/21/97 PACKAGE OUTLINES 16-Lead Plastic DIP SYMBOL A B C D E MIN INCHES MAX 0.300 0.026 .100 typ .010 typ 1.950 0.330 0.254 0.760 MILLIMETERS MIN MAX 7.62 0.36 0.66 2.54 0.25 49.53 8.38 6.45 19.30 0.014 16 1.150 0.290 0.246 0.740 29.21 7.37 6.25 18.80 G F G H 1 H F E A D C B 20-Contact Leadless Chip Carrier (LCC) A H G SYMBOL A B C D E F G H MIN INCHES MAX .040 typ .050 typ 0.055 0.360 0.066 .020 typ 0.028 0.075 MILLIMETERS MIN MAX 1.02 1.14 8.76 1.37 0.56 1.27 1.40 9.14 1.68 0.51 0.71 1.91 B Bottom View Pin 1 0.045 0.345 0.054 0.022 C D F E SPT9687 6 3/21/97 PACKAGE OUTLINES 20-Lead Plastic Leaded Chip Carrier (PLCC) A B Pin 1 G N TOP VIEW F E MO INCHES SYMBOL MIN MAX .045 typ 0.350 0.385 0.350 0.385 0.042 0.165 0.085 0.025 0.015 0.026 0.013 0.290 0.356 0.395 0.356 0.395 0.056 0.180 0.110 0.040 0.025 0.032 0.021 0.050 0.330 A B C D E F G H I J K L M N O MILLIMETERS MIN MAX 1.14 8.89 9.78 8.89 9.78 1.07 4.19 2.16 0.64 0.38 0.66 0.33 7.37 9.04 10.03 9.04 10.03 1.42 4.57 2.79 1.02 0.64 0.81 0.53 1.27 8.38 L C D K J I H Pin 1 BOTTOM VIEW 16-Lead Small Outline Integrated Circuit (SOIC) SYMBOL A B C D E F G H I MIN INCHES MAX 0.157 0.244 0.393 0.0192 0.0098 0.068 0.0098 0.061 MILLIMETERS MIN MAX 3.81 5.84 9.80 1.27 Typ 0.35 0.127 1.55 0.19 1.40 3.99 6.20 9.98 0.49 0.25 1.73 0.25 1.55 0.150 0.230 0.386 .050 Typ 0.0138 0.004 0.061 0.0075 0.055 16 AB 1 C G F D E SPT9687 7 3/21/97 I H PIN ASSIGNMENTS QA 1 QA 2 GNDA 3 LE A 4 LE A 5 VEE 6 -IN A 7 +IN A 8 PDIP/SOIC 16 QB 15 QB 14 GNDB 13 LE B 12 LEB 11 VCC 10 -INB 9 +INB PIN FUNCTIONS NAME QA QA GNDA LEA LE A VEE -INA +INA +INB 18 GND B 17 LE B FUNCTION Output A Inverted Output A Ground A Latch Enable A Inverted Latch Enable A Negative Supply Voltage Inverting Input A Non-Inverting Input A Non-Inverting Input B Inverting Input B Positive Supply Voltage Latch Enabled B Inverted Latch Enable B Ground B Output B Inverted Output B QA QA N/C QB Q B 3 GNDA 4 LE A 5 N/C 6 TOP VIEW 2 1 20 19 -INB VCC LEB LE B GNDB QB QB 16 N/C 15 LE B 14 VCC LE A 7 VEE 8 9 10 11 12 13 -IN A +INA N/C +IN B -IN B LCC/PLCC ORDERING INFORMATION PART NUMBER SPT9687SIN SPT9687SIP SPT9687SIC SPT9687SIS SPT9687SCU Temperature Range -25 to +85 C -25 to +85 C -25 to +85 C -25 to +85 C +25 C PACKAGE TYPE 16L PDIP 20L PLCC 20C LCC 16L SOIC Die* *Please see the die specification for guaranteed electrical performance. SPT9687 8 3/21/97 |
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